Programmable logic devices (PLDs) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
Another type of PLD is the Complex Programmable Logic Device, or CPLD. A CPLD includes two or more “function blocks” connected together and to input/output (I/O) resources by an interconnect switch matrix. Each function block of the CPLD includes a two-level AND/OR structure similar to those used in Programmable Logic Arrays (PLAs) and Programmable Array Logic (PAL) devices. In some CPLDs, configuration data is stored on-chip in non-volatile memory. In other CPLDs, configuration data is stored on-chip in non-volatile memory, then downloaded to volatile memory as part of an initial configuration sequence.
For all of these programmable logic devices (PLDs), the functionality of the device is controlled by data bits provided to the device for that purpose. The data bits can be stored in volatile memory (e.g., static memory cells, as in FPGAs and some CPLDs), in non-volatile memory (e.g., FLASH memory, as in some CPLDs), or in any other type of memory cell.
Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example, using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include, but are not limited to, these exemplary devices, as well as encompassing devices that are only partially programmable.
Before programming a PLD with data bits, the PLD is typically reset, which sets the device to a known initial condition. For example, a PLD is reset when it is first powered on to initialize the logic, memory, and routing to a known state, and then the data bits are loaded into the PLD to set the logic and any optionally routing and memory. Typically, several modules (i.e. portions of the PLD configured to run an application) are loaded into the PLD. In some instances, it is desirable to reconfigure one module, while not reconfiguring the other modules. One way to do this would be to halt operation of the entire PLD, reset the PLD, and load in a complete set of instructions for all the modules. This is very inefficient and disrupts operation of the modules that are not being reconfigured (“fixed modules”).
Another approach is to allow the fixed modules to continue running while only reconfigured modules are loaded. Reconfiguring a selected module while allowing the remainder of the PLD to continue operating is called “active partial reconfiguration.” However, whenever a reconfigured module has completed loading, the previous state of the flip-flops are preserved and may not contain the proper state to correctly operate the reconfigured module.
Additionally, conventional partial active reconfiguration methods typically need to detect when the reconfigured module is available for use, and many clock cycles of the PLD could be wasted to poll the state of the reconfigured module to determine if it is active or not, and whether it needs to be reset. Once the state is detected, the module is reset, if needed. However, the reconfigured module could have been inactive for some time, resulting in a loss of processing power. Even worse, the reconfigured module could have executed erroneous commands because the initial state of the module was unknown before the reset.
Therefore, it is desirable to reset a reconfigurable module of a programmable logic device while other modules of the programmable logic device remain active.